The present application relates generally to semiconductor devices, and more specifically to fin field effect transistors and their methods of production.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. The fins are etched to a depth to provide a desired height for an active channel region and to include adequate sub-fin isolation for a particular device. A gate structure is deposited over the channel region to contact multiple surfaces of each fin to form a multi-gate architecture.
As device dimensions scale, including the dimensions between adjacent devices or features, associated processing has become increasingly complex. Isolation doping of the sub-fin region, for example, is difficult to perform without affecting doping of the active channel region, and hence the carrier mobility therein. Furthermore, as the intra fin spacing decreases, the localized introduction of dopants into the fins, and the integration of conformal masking layers that are typically used to form devices having complementary polarities, has become increasingly challenging.